An output driver (sometimes called an "output buffer") is an electronic circuit that furnishes one or more output signals at voltage/current levels suitable to drive a load such as another circuit, or a bus. Multiple different output driver structures have been realized using complementary field effect transistor (CMOS) technology. A CMOS output driver uses both P-channel and N-channel insulated-gate field effect transistors (FETs). By using CMOS technology, an output driver circuit can typically be designed to consume a relatively small amount of power.
One possible application for a CMOS output driver circuit is an interface between a digital logic circuit and a bus operating at transistor-transistor logic (TTL) voltage levels. The commercially available 74FCT245, 74FCT16245, 74FCT162245, 74FCT163245, 74FCT164245, 74FCT245T, and 74FCT3245 are examples of parts containing CMOS output driver circuits. Due to the use of both P-channel and N-channel FETs in a CMOS output driver circuit, the internal circuitry of the typical CMOS output driver circuit operates at CMOS digital voltage levels, i.e. a CMOS high digital logic voltage level is usually a voltage between the Vcc supply voltage and Vcc/2 whereas a CMOS low digital logic voltage level is usually a voltage between ground and Vcc/2. The signal output from the CMOS output driver and onto the bus must, however, drive the bus at the appropriate voltage and current levels to satisfy requirements of any TTL and/or CMOS digital logic circuitry connected to the bus. This means that the CMOS output driver circuit must output a voltage between the minimum V.sub.OH (minimum TTL V.sub.OH or the minimum high digital logic level output voltage for TTL logic is 2.4 volts) to Vcc (TTL Vcc is 5.0 volts typically plus or minus ten percent) in order to output a high digital logic level onto the bus. This also means, however, that the CMOS output driver must output a voltage between ground and the maximum V.sub.OL (maximum TTL V.sub.OL or the maximum low digital logic level output voltage for TTL is 0.5 volts) in order to drive the bus with a low digital logic voltage level.
FIG. 1 shows a conventional cmos output driver circuit 1 having a data input terminal 2, an enable/disable input terminal 3, a data output terminal 4, four digital logic gates 5-8, a first N-channel output transistor 9, a second N-channel output transistor 10, a resistive element 11, an internal high V.sub.HI voltage supply line 12, and an internal low V.sub.LI voltage supply line 13. Digital logic gates 5-8 are shown surrounded by a dashed box 14 into which the internal high and internal low voltage supply lines 12 and 13 extend. This indicates that digital logic gates 5-8 are powered by the internal high and low voltage supply lines 12 and 13. The resistive element 11 is coupled between the V.sub.HI voltage supply line 12 and the drain of the first N-channel output transistor 9. Both the source of the first N-channel output transistor 9 and the drain of the second N-channel output transistor 10 are connected to the data output terminal 4. The source of the second N-channel output transistor 10 is connected to the internal low V.sub.LI voltage supply line 13.
In operation, interconnected gates 5-8 receive digital logic voltage level signals on both the data input terminal 2 and also on the enable/disable input terminal 3. From these digital voltage level signals, gates 5-8 generate appropriate control signals V.sub.UP and V.sub.DN to control the first and second output transistors 9 and 10 respectively so that the data output terminal 4 is either coupled to the internal high V.sub.HI voltage supply line 12, coupled to the internal low V.sub.LI voltage supply line 13, or is decoupled altogether from both internal voltage supply lines 12 and 13.
If, for example, the conventional output driver of FIG. 1 is enabled by a high digital logic voltage level signal being present on the enable/disable input terminal 3, then gates 5-8 cause the data output terminal 4 to be driven to a digital logic voltage level corresponding to the digital logic voltage level present on the data input terminal 2. If, for example, a digital logic level high signal is present on data input terminal 2, then the first N-channel transistor 9 is turned on and the second N-channel transistor 10 is turned off. The data output terminal 4 is therefore coupled to the internal high V.sub.HI voltage supply line 12 through conductive output transistor 9 and resistive element 11 and is decoupled from the internal low V.sub.LI voltage supply line 13 by nonconductive second output transistor 10. If, on the other hand, a digital logic level low signal is present on data input terminal 2, then the first N-channel output transistor 9 is turned off and the second N-channel output transistor 10 is turned on. The data output terminal 4 is therefore decoupled from the internal high V.sub.HI voltage supply line 12 by nonconductive first output transistor 9 and is coupled through the conductive second output transistor 10 to the internal low V.sub.LI supply line 13.
In conditions where the conventional output driver of FIG. 1 is to be disabled by a low digital logic voltage level signal present on the enable/disable input terminal 3, gates 5-8 cause the data output terminal 4 to be simultaneously decoupled from both internal voltage supply lines 12 and 13 regardless of the digital logic voltage level present on the data input terminal 2. A low digital logic level signal present on the enable/disable input terminal 3 causes both the first and the second N-channel output transistors 9 and 10 to be turned off, thereby decoupling the data output terminal 4 from both the internal voltage supply lines 12 and 13 regardless of the digital logic voltage level of a signal present on data input terminal 2.
As the switching speed of such conventional output driver circuits increases due to ever decreasing transistor geometries and due to other improvements in semiconductor processing technology, a number of problems are experienced with the above-described output driver structure.
A first problem is voltage "bounce" on the voltage supply lines. A physical electrical connection has an associated intrinsic inductance. An inductance therefore necessarily exists due to the physical electrical connection from the circuitry of the output driver, through the voltage supply lines on the integrated circuit die of the output driver, through the electrical connections connecting the integrated circuit die of the output driver to the integrated circuit package housing the output driver, and through the electrical connections of the package which provide electrical connection to an externally accessible physical terminal on the exterior of the package. Accordingly, an inductance 12a is illustrated in FIG. 1 as existing between an external high V.sub.HE voltage supply terminal 12b and the internal high V.sub.HI voltage supply line 12. Similarly, an inductance 13a is illustrated as existing between an external Low V.sub.LE voltage supply terminal 13b and the internal low V.sub.LI voltage supply line 13.
Letting "dI/dt" represent the time rate of change of the current "I" flowing through an inductance of magnitude "L", the magnitude of the voltage change "V" across the inductance is given by: V=L dI/dt. It is therefore seen that the magnitude of the voltage change or "bounce" on an internal voltage supply line is equal to the product of the voltage supply line inductance and the speed at which a current of a given magnitude flowing through the voltage supply line inductance changes. Accordingly, turning the N-channel output transistors of an output driver on and off in smaller and smaller periods of time to decrease V.sub.IN to V.sub.OUT propagation delay results in a larger and larger bounce. Bounce appearing on the internal high V.sub.HI voltage supply line is commonly called "supply line bounce". Bounce appearing on the internal low V.sub.LI supply line is commonly called "ground bounce".
Special attention should be paid to bounce when an integrated circuit contains a number of output drivers arranged in parallel, as in an application in which a bus is being driven by output drivers. In this case, many or all the output drivers may be commonly switched together at the same time. Accordingly, the magnitude of the current being switched over an internal voltage supply line of the integrated circuit may be large and the resultant magnitude of the voltage bounce on the internal voltage supply line may be severe.
A second problem associated with the above-described conventional output driver structure is known as "live-insertion". A CMOS output driver may, for example, be fabricated on an N-type semiconductor substrate. P-type wells are formed in the N-type substrate and the sources and drains of the N-channel output transistors are formed in the P-type wells. The N-type substrate is coupled to the high voltage supply to prevent the PN junctions between the P-wells and the N-type substrate from becoming forward biased. FIG. 2 is a simplified cross-sectional illustration of a part of the conventional output driver of FIG. 1.
A problem occurs in bus applications, however, wherein the data output terminal of an unpowered output driver must be capable of being physically placed in electrical contact, either directly or indirectly via an intermediate conducting mechanism, with a "live" bus line without detrimentally affecting the operation of either the bus line or the output driver. This situation commonly occurs when a printed circuit board carrying a CMOS output driver is plugged into a connector of a live bus on the backplane of a computer. Plugging the printed circuit board into the backplane couples the power and ground supply voltages to the output driver circuit and also couples a live bus line on the backplane to the data output terminal of the output driver integrated circuit. The internal high voltage supply line of the output driver integrated circuit may, therefore, not yet be powered for a period of time when the data output terminal is already connected to a "live" signal on the bus line of the backplane. If any P-region such as a P-well or a source or a drain of a P-channel transistor of a CMOS gate disposed in the N-type substrate of the output driver is connected to the data output terminal of the output driver during this time, a PN junction between the P region and the N-type substrate may become forward biased when a high digital logic voltage level is present on the backplane bus line. This forward biasing cannot be tolerated.
A prior art solution (see FIG. 2) to this problem is to tie all the P-wells permanently to the internal low supply voltage line and not to connect any other P regions in the output driver to the data output terminal. Permanently grounding the P-well containing the first output N-channel transistor in the above-mentioned output driver, however, detrimentally affects the minimum V.sub.OH ; that is V.sub.OH minimum is lower in amplitude than desired. Accordingly, it is desirable to find a way to prevent this unwanted lowering of V.sub.OH minimum.
Another prior art solution is to add a process step which modifies the back biased threshold voltage in the first output transistor to achieve a higher output voltage when the source to bulk voltage equals, for example, 2.4 volts. Unfortunately, adding a process step increases the cost of the device.